1. Field of the Invention
The present invention relates to a delay circuit delaying an input signal, and specifically, to a delay circuit with a timing adjustment function.
2. Description of the Background Art
A general configuration of a delay circuit delaying an input signal is to employ a plurality of delay elements connected in series. For example, an inverter formed of a P-channel MOS transistor and an N-channel MOS transistor connected in series is generally used as a delay element in a semiconductor device of CMOS (Complementary Metal-Oxide Semiconductor device) structure. An input signal can be delayed for a desired delay time by selecting the number of stages of the delay elements in the delay circuit.
On the other hand, it is difficult to render the characteristics of the elements forming the delay element uniform due to variations in a manufacturing process or fluctuations in the supply voltage or the ambient temperature, and thus, an accurate delay of input signal is undesirably hindered. For example, when the above-mentioned delay circuit is used for adjusting the timing of each signal in a signal read/write control circuit of DRAM (Dynamic Random-Access Memory), which is based on a row address strobe (RAS) access that uses RAS, the timing of RAS access changes as the set delay time changes, which in turn results in the degradation of the sensitivity.
In view of the foregoing, various delay circuits that can delay an input signal accurately have been proposed recently. Such delay circuits are disclosed, for example, in Japanese Patent Laying-Open No. 11-274904, Japanese Patent Laying-Open No. 2000-31818, Japanese Patent Laying-Open No. 2000-341099, and Japanese Patent Laying-Open No. 2000-357951.
As one example, a delay circuit formed of a delay section formed of a plurality of delay elements and a phase locked loop (PLL) circuit can be found.
The PLL circuit herein is a circuit for generating a clock synchronized for cooperatively operating a plurality of internal circuits mounted on the same system. The PLL circuit mainly includes a phase comparator comparing the phase of an input clock and that of a feed back clock being fed back from an internal circuit, a charge pump circuit providing a control signal based on the comparison result of the phase comparator, and a voltage controlled oscillator (VCO) supplying to the internal circuit an output signal having a frequency corresponding to the control signal.
The voltage controlled oscillator has a ring oscillator formed of the odd numbers of delay elements coupled in a ring form, and determines the operating current of each delay element in accordance with a control circuit. As a result, a clock with an oscillation frequency corresponding to the operating current of the delay element is output from the ring oscillator.
In the delay circuit in the configuration above, the voltage controlled oscillator, in response to a control signal from the charge pump circuit, changes an oscillation frequency fosc, i.e., the frequency of the output clock, and feeds back the output clock to the phase comparator. This series of operations is performed until the phase of the output clock and that of the feedback clock are coincident with each other. When the PLL circuit enters a so-called locked state, i.e., when the phase of the output clock and that of the feedback clock are coincident, the control signal takes on a certain fixed value, and the delay amount of each delay element in the voltage controlled oscillator is fixed to a prescribed value.
The delay section is configured with the same delay element as the voltage controlled oscillator, and controls the delay time in response to the charge pump circuit supplying the control signal to delay a data signal provided to the delay section. When the PLL circuit enters a locked state, each delay element receives a fixed control signal and thus the delay amount thereof is fixed to the same delay amount as in the voltage controlled oscillator.
Accordingly, since the delay amount of the delay section can be set with the accuracy ensured by the PLL circuit, it is possible to perform a timing adjustment without being affected by the variations in operating environment such as the supply voltage and the temperature as well as variations in processing.
In such a delay circuit, the PLL circuit has an output frequency range that can maintain the locked state (hereinafter also referred to as a lock range), and the delay time in the delay unit is also determined by this lock range. Note that the lock range of the PLL circuit largely depends on the output frequency range of the voltage controlled oscillator therein.
The oscillation frequency fosc of the voltage controlled oscillator changes in the locked state relative to the voltage level of the control signal being input. The control signal is generated based on the result of phase comparison performed by the phase comparator, and its voltage ranges from the ground voltage level to the vicinity of the ground voltage level.
In order to keep a wide lock range, the PLL circuit must be able to maintain the locked state in a wide control voltage range. Practically, however, when the control signal approaches close to the ground voltage level or the supply voltage level, jitter (phase shift) occurs in the generated clock due to the effect of noise superimposed on the supply voltage and the like, and thus the locked state can not be maintained. Accordingly, with a conventional delay circuit, it has been difficult to perform the timing adjustment stably.